It would be desirable to have a distributing network that is designed to send the signal of one input port to N output ports simultaneously, with the following additional requirements (or constraints):    1. The distributing network should be broadband, ideally from DC to infinite frequency (DC=direct current).    2. Each of the N output ports of the distributing network should be individually selectable as transmitting or not transmitting one.    3. As minimum requirement, the input port and all the M (1≦M≦N) output ports of the distributing network selected to transmit should be impedance matched.    4. As additional requirement, not only the M transmitting ports but also the remaining ones should be impedance matched, i.e. all the N+1 ports of the distributing network should be impedance matched, independently on which port(s) is(are) transmitting.    5. The insertion loss of the distributing network should be reduced (or even minimized).    6. The temperature dependency of the distributing network should be reduced (or even minimized).    7. The linearity of the distributing network should be increased (or even maximized).    8. The sensitivity of the distributing network to manufacturing process variations and the requirement of postproduction alignment should be reduced (or even minimized).
One possible structure that holds some—but not all—of the requirements listed above is the single pole N throw (SPNT) switch, wherein within this context, N is an integer multiple and stands for “multiple”. A detailed description of the SPNT switch can be found in Roberto Sorrentino, Giovanni Bianchi: Microwave and RF Engineering, Ch. 10, pp. 363-389. The main drawback of the SPNT switch is that only one output port at the time can be selected among the available N output ports.
Thus, at least requirement 2 stating that each of the N output ports should be individually selectable as transmitting or not transmitting one is not satisfied.
One other circuit which satisfies some—but again not all—the requirements listed above is the N-output splitter 10, schematized in FIG. 1. It consists of N+1 equal valued resistors, indicated in FIG. 1 as R1 to RN+1, and N+1 Ports, indicated in FIG. 1 as P1 to PN+1. The N+1 equal valued R1 to RN+1 resistors connect the N+1 Ports P1 to PN+1 to a common node 12. Thereby, the equal valued resistors R1 to RN+1 comprise fixed or constant resistance values.
The condition for simultaneously matching all of the N+1 ports P1 to PN+1 (i.e., for fulfilling requirement 3 stating that the input port and all of the M output ports selected to transmit should be impedance matched and requirement 4 stating that not only the M transmitting ports but also the remaining ones should be impedance matched) is:
                              R          k                =                                            N              -              1                                      N              +              1                                ⁢                      R            0                    ⁢                                          ⁢                      (                          1              ≤              k              ≤                              N                +                1                                      )                                              (        1        )            where R0 is the reference impedance, normally equal to 50Ω.
Under the condition described by equation (1) the scattering parameters of the network in FIG. 1 are
                              s          hk                =                              1            N                    ⁢                                          ⁢                      (                                          1                ≤                h                            ,                              k                ≤                                  N                  +                  1                                            ,                              h                ≠                k                                      )                                              (        2        )                                          s          hk                =                  0          ⁢                                          ⁢                      (                          1              ≤              k              ≤                              N                +                1                                      )                                              (        3        )            as all the ports are totally equivalent.
Equation (3) confirms the impedance matching of the structure and needs no further comments. Equation (2) states that the splitter 10 transmits the input power to each of its N output ports P2 to PN+1 with an attenuation in linear units equal to the reciprocal of the number N of output ports P2 to PN+1 itself. From equation (2) it also follows that the ratio between the input power PIN (present at the input port P1) and the output power POUT globally transmitted to the output ports P2 to PN+1 is
                                          P            OUT                                P            IN                          =                                            ∑                              k                =                2                                            N                +                1                                      ⁢                                                                            s                                      k                    ,                    1                                                                              2                                =                                                    ∑                                  k                  =                  2                                                  N                  +                  1                                            ⁢                                                                                      1                    N                                                                    2                                      =                          1              N                                                          (        4        )            
In other words, only 1/N of the available input power PIN is shared between the output ports P2 to PN+1, where the remaining (N−1)/N of the available input power PIN is dissipated inside the structure 10. That could be in contrast with requirement 5 stating that the insertion loss of the distribution network should be reduced (or even minimized). On the other side, the only way to realize a non-dissipative N-way power divider structure is by using reactive elements instead of resistors. One of such possibility's is based on the so called Wilkinson power divider, as described in Giovanni Bianchi: Microwave and RF Engineering, Ch. 7, pp. 205-209. Unfortunately, reactive elements are inherently frequency-depending. Therefore, non-dissipative distributed networks can only be realized with relative bandwidth of relatively few octaves.
FIG. 2 lists in a table resistance values and transmission coefficients of N-way power splitters. In other words, FIG. 2 lists in a table the resistance values of the fixed equal valued resistors (assuming R0=50Ω) and the input-output transmission coefficients for power splitters having a number of output ports from 1 to 16 (the 1-output power splitter is a trivial structure consisting of a direct input-output connection).
An additional requirement not fulfilled by the structure shown in FIG. 1 is requirement 2 stating that each of the N output ports P2 to PN+1 should be individually selectable as transmitting or not transmitting one.